1. Field of the Invention
The present invention relates to a method of forming a non-volatile semiconductor memory which comprises the region of a peripheral circuit and a cell region on a semiconductor substrate, which has an advanced device isolating characteristic.
2. Description of the Related Art
The conventional method of manufacturing a flash memory will be explained, with reference to drawings.
FIG. 1 shows the configuration of the conventional flash memory, fabricated at the halfway manufacturing stage, just before the step of making an interconnection in a cell region. Source and drain regions are formed in diffused layer regions 301. Floating gates 303 are formed in hatched regions in the figure. Word lines 304, which also play a role as control electrodes, are formed over the floating gates 303. Device isolating oxide regions 302 are formed in the respective regions, between the adjacent left and right regions of diffused layer 301. Tunnel oxides, each playing a role for the generation of a channel region, are formed right under the floating gates 303, but not in the device isolating oxide regions 302.
The conventional method of manufacturing the flash memory will be explained below, with reference to process cross sections in FIGS. 2A to 9A and 2B to 9B. In these figures, FIGS. 2A to 9A show cross sections of the region of the peripheral circuit of the flash memory, whereas FIGS. 2B to 9B show cross sections of a cell unit region of the flash memory. No transistors are formed in the cell unit region, whereas necessary transistors are formed in the region of the peripheral circuit.
Firstly, device isolating oxide layers 401, each having a thickness of approximately 4000 to 5000 angstroms, are formed on a semiconductor substrate by using the LOCOS (Local Oxidation of Silicon) method, etc., followed by the formation of a tunnel oxide layer 403, having a thickness of 100 angstroms or less, in a device region of the flash memory. A polysilicon layer 402 is deposited next, all over the surface (see FIG. 2). Floating gates are formed from the polysilicon layer 402, in the next step. Phosphorous (p), generally, is implanted next, in the polysilicon layer 402, which has a thickness of approximately 1500 angstroms.
Next, a photo resist (not shown in figures) is patterned by utilizing the conventional photographic process. Thereafter, floating gates 404 are formed by etching the polysilicon (see FIG. 3B). At this time, with the region of the peripheral circuit not covered by a resist, the polysilicon layer 402 of the region is removed (FIG. 3A).
Thereafter, an insulation layer 405 is deposited all over the surface. The insulation layer 405 is used to isolate control gates from respective floating gates. The insulation layer 405, which is an ordinary multiple layered structure of silicon oxide layer/silicon nitride layer/silicon oxide layer, has a thickness of 180 angstroms or less, if it is converted into the thickness of an oxide layer. To remove the insulation layer 405 in the region of the peripheral circuit, a resist 406 is coated next, all over the cell unit region (FIG. 4B).
The insulation layer 405, in the region of the peripheral circuit, is then etched. At this time, a gate oxide layer is formed on the region, where the device isolating oxide layers 401 do not exist. Therefore, the insulation layer 405 formed over the region has to be completely removed. Accordingly, it needs to be adequately over-etched. However, the etching selectivity of the insulation layer 405 to the device isolating oxide layer 401, which is located under the insulation layer 405, cannot be set to a high value. This causes a partial loss of the device isolating oxide layer 401 in the region of the peripheral circuit.
Thereafter, a gate oxide layer 407, used for making up the transistors in the region of the peripheral circuit, is formed by utilizing an ordinary, thermal oxidation process.
After removal of the resist 406, a polysilicon layer 408, in which phosphorous has been implanted and a silicide layer 409 are deposited systematically all over the substrate. Each of them has a thickness of approximately 1500 angstroms. The polysilicon layer 408 and the silicide layer 409 are to become gate electrodes of transistors in the region of the peripheral circuit and control electrodes of transistors in the cell unit region, at the same time. Thereafter, in order to etch so as to form cell gates (hereafter, referred to as cell gate etching), the entire region of the peripheral circuit and predetermined places in the cell unit region, are covered with a resist 410 (FIG. 6A). Note that no electrode is formed in the cross section of the cell unit region, as shown in FIG. 6B. Accordingly, a resist 410 is not prepared, as shown in the structure in FIG. 6B.
To form electrodes in the cell unit region, cell gate etching is performed next. The state after etching is shown in FIG. 7. It is noted that no cell gate is shown in the region because FIG. 7B shows a cross section along the line A-A' in FIG. 1.
Thereafter, source and drain regions (not shown in figures) are formed, in the cell unit region. All cell unit regions, and predetermined places, where gates are to be formed, are covered with a resist 411 (see FIG. 8). Gate electrodes are then formed in the region of the peripheral circuit, by etching (FIG. 9A).
Source and drain regions are formed next, in the region of the peripheral circuit and thereby, transistors are completed in the region of the peripheral circuit. A flash memory is completed next, through an ordinary contact construction process and an ordinary interconnection process.
However, in the above conventional techniques, removing the polysilicon layers of the floating gates, in the region of the peripheral circuit and removing the polysilocon layers of the floating gates, in the cell region, are performed at the same time (see FIG. 3). This causes a deposition of an insulation layer directly on top of the device isolating oxide layers, in the region of the peripheral circuit (FIG. 4A). However, in the subsequent etching step of removing the insulation layer, in the region of the peripheral circuit, the etching selectivity of the insulation layer to the device isolating oxide layer, which is located under the insulation layer, cannot be set to a high value. This causes a partial loss of the device isolating oxide layers in the region of the peripheral circuit (see FIG. 5A). This loss results in a deterioration of the device isolating properties on the polysilicon interconnects, which run on the device isolating layers in the region of the peripheral circuit. In addition to that, in the subsequent step of implanting ions and forming source and drain regions of transistors, in the region of the peripheral circuit. The ions possibly pass through the device isolating oxide layers, which make it easier to generate a channel, right under each device isolating oxide layer. This causes further degradation to the device isolating properties.